1. Field of the Invention
This invention relates to field emission devices, and more particularly to field emission triodes (FETs) in which an anode is spaced above an electron-emitting cathode, with current flow between the two controlled by a lateral gate.
2. Description of the Related Art
Vacuum FETs that use semiconductor material and have some significant advantages over transistors have been developed recently. They are operable over a wide temperature range, have very fast speeds for both analog and digital applications, high power efficiency, small and lightweight packages, low cost and resistance to radiation damage. FET developments are described, for example, in Skidmore, "Industry News--The Comeback of the Vacuum Tube: Will Semiconductor Versions Supplement Transistors?", Semiconductor International, August, 1988, pages 15-18, and Spindt, et al. "Field Emission Array Development", 33rd Int'l. Field Emission Symposium, July, 1986, pages 1-11.
A FET consists of an electron-emitting cathode, an anode which collects electrons given off by the cathode, and a current controlling gate. The cathode terminates in a sharp tip which provides a high electric field concentration. A multiple array of FETs is normally fabricated at one time and operated in parallel for a higher power capacity, with a single common anode structure provided for all of the cathode emitters in the array. Cavity molding techniques for forming the pointed cathodes are described in U.S. Pat. No. 4,307,507 to Gray, et al., and in U.S. patent application Ser. No. 457,208, filed Dec. 26, 1989 by Bardai, et al. and assigned to Hughes Aircraft Company, the assignee of the present invention.
An overall FET fabrication process is described in U.S. Pat. No. 4,943,343 to Bardai et al., also assigned to Hughes Aircraft Company. In this patent a conical gate structure is formed over the conical cathode and spaced therefrom by an insulating layer, while a conical anode structure is formed over the gate and spaced therefrom by another insulating layer. The central portions of the anode and gate structures are then removed, along with the nearby portions of the insulating layers, to produce a final FET structure in which the gate and anode are progressively above but laterally spaced from the cathode. A distinct advantage of this approach is that it significantly reduces the spacing between the cathode and gate, thereby making it possible to operate with lower gate voltages on the order of 10 volts. However, the anode's lateral offset from the cathode emission tip requires a much higher anode voltage, and results in an excessive capture of electrons by the gate.
Another fabrication technique is described in U.S. patent application Ser. No. 552,643, filed Jul. 16, 1990 by Longo et al. and assigned to Hughes Aircraft Company. In this application the gate is a horizontal layer formed upon a vertical insulating wall lateral to the cathode, while the anode is another horizontal layer spaced above the gate by a second wall and again laterally offset from the cathode. A conductive cover plate is mechanically bonded over the top of the anode structure, with both the anode and the cover plate receiving electrons emitted from the cathode. The separate plate and its mechanical bonding process cannot be accurately controlled to very small dimensions, and results in a cathode-anode gap of 50 microns or greater. Furthermore the anode support structure requires a considerable amount of excess processing to fabricate and is not integrable with the fabrication of other circuitry on the same chip.
The desirability of a small clearance between the anode and the cathode emission tip has been recognized. A small clearance requires a proportionately smaller anode voltage to establish the same electric field and emission current; the smaller anode voltage yields a similar reduction in power dissipation. For example, the Skidmore article mentioned above mentions a spacing of 0.5 micron. However, neither this article nor any other of the references proposes any practical way to achieve anything near such a small spacing.
Another technology that is of interest to the present invention, but has developed independently of the FET area, is that of conductive air bridges. Such structures have been used extensively for crossovers of metallic interconnection lines in GaAs analog devices. They are used when the metallization pattern requires that two lead lines cross over each other without electrically connecting. With an air bridge, a span is formed in one of the lines so that it bridges the other line, with air separating the two. As opposed to crossovers that are electrically isolated by means of a dielectric layer between the two lines, which is typical of digital devices, air bridges exhibit low parasitic capacitance, an immunity to edge profile problems and an ability to support a substantial current. They are described, for example, in Williams, Gallium Arsenide Processing Techniques, Tech House, Inc., 1984, pages 334-339.
It is desirable to keep air bridge crossover profiles low to maintain a more planar circuit surface. To this end the clearance between the underlying conductor and the bridging conductor is held to not more than one or two microns. The lower limit for the clearance is established by the operating voltages expected for the two lines, and must be kept large enough to maintain an air insulation between the two and prevent any current flow from one line to the other. Since the opposed surfaces of both conductors are normally flat, the electric field between the two will generally be uniform and not exhibit significant concentrations at any one point; this allows for a close spacing between the two lines.